Storage device and accessing method

ABSTRACT

In order to access a memory cell array ( 1 ), an address translation table which stores a correspondence between logical and physical addresses, and an empty block table which specifies locations of empty blocks, are stored in an arbitrary block of the memory cell array ( 1 ) itself. In the case of reading data from the memory cell array ( 1 ), a physical address to read data is attained with reference to the address translation table stored in the memory cell array ( 1 ). Meanwhile, in the case of writing data, an empty block is detected from the empty block table stored in the memory cell array ( 1 ), and data is written in the empty block. Moreover, the address translation table and the empty block table which have been updated are written in another empty block.

TECHNICAL FIELD

This invention relates to a storage device and an accessing method, andparticularly to a block erase type storage device and an accessingmethod for the same.

BACKGROUND ART

A block erase type storage device is known which comprises a block erasetype storage medium such as a flash memory, and which reads and writesinformation under the control of a central processing unit (CPU) and adedicated controller.

The block erase type storage medium indicates such a storage medium thatthe storage contents of a writing target area need to be erased inadvance in order to write data therein and an erasing process can beperformed only in units (generally called blocks) equal to or largerthan the smallest unit (generally called a page, a segment or the like)of the storage capacity dealt in a writing process.

In order to manage an external access, the block erase type storagedevice comprises an SRAM (Static Random Access Memory) or the like whichstores an empty block table in which information representing thelocations of empty blocks is stored and an address translation table inwhich information showing the correspondence between logical andphysical addresses is stored.

Upon reception of a write request, the block erase type storage devicefinds an empty block registered in the empty block table, writes data inthe found block, adds the correspondence between the physical andlogical addresses of the block to the address translation table, andfurthermore, erases the block from the empty block table.

Moreover, upon reception of a read request, the block erase type storagedevice searches the address translation table while using the logicaladdress of to-be-read data as a key, discriminates the physical addressof the location at which the to-be-read data has been stored, and readsthe data from that location.

In to such a storage device, the volume of the entire storage deviceincreases according to the volume occupied by the SRAM. Due to this,such a storage device when used for purposes which require a smallvolume as in the case of a JEIDA/PCMCIA card, etc., needs a volumesuppressing idea.

Furthermore, the SRAM consumes a large amount of power, and if the SRAMis used to store a variety of tables, the amount of power consumed bythe entire storage device increases, entailing a drawback of the storagedevice becoming unsuitable for being applied to purposes which requirelow power consumption as in the case of a JEIDA/PCMCIA card, etc.

DISCLOSURE OF INVENTION

This invention has been made in consideration of the above-describedcircumstances, and an object thereof is to provide a block erase typestorage device of a small volume and low power consumption and anaccessing method for the same.

A storage device according to the first aspect of this invention havingthe above object is characterized by comprising:

storage means (1), including a plurality of memory blocks to whichphysical addresses have been assigned;

erasure means (1 e) for batch erasing of stored data from the storagemeans in units of memory blocks; and

writing means (4X, 4B, 5, 20), to which data and logical addresses areinput, for determining locations where the data is to be stored in thestorage means and for writing the data in the locations;

wherein the storage means stores an address translation table whichstores information showing a correspondence between the logicaladdresses and physical addresses of the storage means, and

the writing means comprises means (4X, 4B, 5, 20) for adding, to theaddress translation table, information showing a correspondence betweenphysical addresses of the locations where the data has been written andthe input logical addresses, or for updating the address translationtable.

According to the storage device having this structure, the addresstranslation table is stored in the storage means which is a block erasetype storage medium. Therefore, a storage medium such as an SRAM or thelike for storing the address translation table is not required inaddition to the aforementioned storage means. This ensures a block erasetype storage device whose volume is relatively small and whose powerconsumption is low.

The above-described storage device may further comprise reading means(4X, 4B, 5, 20) including:

means (20) for storing a physical address of a block in which theaddress translation table has been written;

physical address reading means (4X, 4B, 5, 20) for accessing the blockwhich contains the address translation table stored therein and forreading physical addresses corresponding to logical addresses ofto-be-read data; and

means (4X, 4B, 5, 20) for reading and outputting data stored at thephysical addresses read by the physical address reading means.

Using this reading means, the physical addresses of the to-be-read datacan be detected and read from the address translation table stored inthe storage means.

The aforementioned storage means can store an empty block table whichstores information specifying empty blocks containing no data storedtherein.

By employing this structure, the used amount of memory such as an SRAMor the like, utilized in addition to the storage means, can be furtherreduced to promote a reduction in the volume and power consumption.

The empty block table which stores information specifying the emptyblock that has been existed until the data has been stored in the emptyblock is eliminated, and the empty block table which stores informationspecifying empty blocks that remain after the empty block writing meanshas written the data in the empty block is stored in the storage means.By so doing, information on the empty blocks contained in the emptyblock table is updated so that the up-to-date empty block informationcan be attained at any time.

The aforementioned storage means may comprise a plurality of chips orflash memories, for example. In this case, the address translation table(and the empty block table) may be stored in an arbitrary block of anyone of the chips or flash memories. And means may be provided forstoring information showing in which block of which chip the addresstranslation table and the empty block table have been stored.

The storage means stores the address translation table and the emptyblock table in one block.

According to this structure, the number of blocks for storing theaddress translation table and the empty block table can be minimized toone, and the storage capacity of the storage means can be used withefficiency. Moreover, the management of the locations at which thosetables have been stored becomes easy.

Further, a storage device according to the second aspect of thisinvention is characterized by comprising:

storage means (1), including a plurality of memory blocks to whichphysical addresses have been assigned;

erasure means (1 e) for batch erasing of stored data from the storagemeans in units of memory blocks; and

writing means (4X, 4B, 5, 20), to which to-be-written data and logicaladdresses are input, for determining locations where the data is to bestored in the storage means and for writing the data in the locations;

wherein the storage means stores empty block information specifyingempty blocks in which the data is not stored, and

the writing means writes the data in an empty block specified by theempty block information.

According to this structure, the empty block information is stored inthe storage means which is a block erase type storage medium. Therefore,a storage medium such as an SRAM or the like for storing the empty blockinformation is not required in addition to the aforementioned storagemeans. This ensures a block erase type storage device whose volume isrelatively small and whose power consumption is low.

If the writing means further comprises updating means (1 e, 4X, 4B, 5,20) for changing the empty block information stored in the storage meansto the empty block information which specifies information on emptyblocks that remain after the writing means has written the data in theempty block, the empty block information is updated so that theup-to-date empty block information can be attained at any time.

The empty block information may be stored in a portion of each emptyblock, and includes chain information registered to specify anotherempty block in a chain manner. In this case, the writing means maycomprise means (4X, 4B, 5, 20) for detecting an empty block inaccordance with the chain information and for writing the data in theempty block.

According to this structure, one block need not be used to store theempty block table, and the efficiency of use of the storage medium ishigh. Moreover, since a writing target block is specified based on thechain information on empty blocks, the frequency of use of each block isuniformized.

When the empty block information includes the chain information, topempty block storing means (20), etc. may be provided for storing anaddress of a first empty block; data may be written in the empty blockassigned the physical address stored in the top empty block storingmeans; and the contents of the top empty block storing means can beupdated by the chain information registered in the block in which thedata has been written.

In the case where the storing means comprises a flash memory or thelike, its storage area comprises data areas and redundant areas. In thiscase, the chain information can be stored in the redundant areas.

In such a storage device, the chain information is written in theredundant areas of the empty blocks, and the aforementioned data isoverwritten in the empty blocks in which the chain information hasalready been written.

In this case, the data areas and the redundant areas are arranged so asnot to overlap each other in the aforementioned storage area, therebypreventing the chain information from being destroyed due to theoverwriting of the aforementioned data.

Similarly in the storage device according to the second embodiment, thestorage means may comprise a plurality of chips or flash memories, forexample. In this case, the chain information may include informationshowing in which block of which chip the next block has been stored.

An accessing method according to the third aspect of this invention is amethod for accessing a memory of a block erase type in which data can beerased in units of blocks and data can be written in empty blocks fromwhich data has been erased in advance, and the method is characterizedby comprising steps of:

causing the memory itself to store an address translation table whichstores information showing a correspondence between physical addressesassigned to the memory and logical addresses of data;

at a time of supply of to-be-written data and their logical addresses,making a determination based on the address translation table as towhether data has already been written at the logical addresses, and whenit is determined that data exists at the logical addresses, detectingthe empty blocks, writing the data in the empty blocks and erasingblocks containing old data, while when it is determined that no dataexists at the logical addresses, detecting the empty blocks, writing thedata in the empty blocks, and thereafter;

adding information showing a correspondence between physical addressesof the blocks in which the data has been written and the logicaladdresses to the address translation table in the memory, or updatingthe information; and

at a time of supply of logical addresses of to-be-read data, accessingthe address translation table in the memory, detecting physicaladdresses of locations where the data has been written, reading the datafrom the physical addresses, and outputting the data.

An accessing method according to the fourth aspect of this invention isa method for accessing a memory of a block erase type in which data canbe erased in units of blocks and data can be written in empty blocksfrom which data has been erased in advance, and the method ischaracterized by comprising steps of:

causing the memory to store an empty block table specifying the emptyblocks;

at a time of supply of to-be-written data, detecting an empty block onthe basis of the empty block table in the memory, and writing the datain the detected empty block.

With the accessing methods according to the third and fourth aspects,parts of the memory can be used as the address translation table and theempty block table, and another memory such as an SRAM or the like forstoring those tables need not be arranged, which contributes toward areduction in the capacity and power consumption.

An accessing method according to the fifth aspect of this invention is amethod for accessing a memory of a block erase type in which data can beerased in units of blocks and data can be written in empty blocks fromwhich data has been erased in advance, and the method is characterizedby comprising steps of:

causing a block which the memory comprises to store empty blockinformation specifying the empty blocks of the memory;

at a time of supply of to-be-written data, detecting an empty block onthe basis of the empty block information, writing the data in thedetected empty block, newly detecting an empty block on the basis of theempty block information, erasing storage contents of the block in whichthe empty block information has been stored, and writing updated emptyblock information in the newly detected empty block.

With the accessing method according to the fifth aspect, not only partsof the memory can be used as the address translation table and the emptyblock table in order to achieve a reduction in the volume and powerconsumption, but also the empty block information can be updated so thatthe latest empty block information can be attained at any time.

An accessing method according to the sixth aspect of this invention is amethod for accessing a memory of a block erase type in which data can beerased in units of blocks and data can be written in empty blocks fromwhich data has been erased in advance, and the method is characterizedby comprising steps of:

storing, in a portion of each empty block of the memory, empty blockchain information which includes information that sequentially specifiesanother empty block; and

at a time of supply of to-be-written data, detecting a top empty blockin an empty block chain defined by the empty block chain information,and writing the data in the detected empty block.

With the accessing method according to the sixth aspect, a part of thememory can be used as the empty block table. Furthermore, since theempty blocks in which data is to be written are in the order of thechain defined by the chain information, the writing frequency can beuniformized over the entirety of the memory.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram illustrating the basic structure of a storagedevice according to an embodiment of this invention;

FIG. 2 is a diagram illustrating the structure of a memory cell array;

FIG. 3 is a diagram showing the logical structure of a storage area;

FIG. 4 is a diagram exemplifying the structure of an empty block table;

FIG. 5 is a diagram exemplifying the structure of an address translationtable;

FIG. 6 is a flowchart showing a data reading process;

FIG. 7 is a flowchart showing a physical address determining process;

FIG. 8 is a flowchart showing a writing process;

FIG. 9 is a flowchart showing an old data erasing process;

FIG. 10 is a flowchart showing a process for updating the empty blocktable and the address translation table;

FIG. 11 is a conceptual diagram depicting a chain of empty blocks in astorage device according to the second embodiment;

FIG. 12 is a flowchart showing a data writing process in the storagedevice according to the second embodiment; and

FIG. 13 is a flowchart showing a process for updating the empty blockinformation and the address translation table in the storage deviceaccording to the second embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

Storage devices according to the best modes for carrying out thisinvention will now be explained.

(First Embodiment)

A storage device according to this embodiment, which stores an addresstranslation table, etc. in a flash memory unit itself, comprises theflash memory unit 10 and a controller 20, as illustrated in FIG. 1.

The flash memory unit 10 comprises a memory cell array 1, an I/O buffer2, an X address buffer 3X, a block address buffer 3B, an X addressdecoder 4X, a block address decoder 4B, a control circuit 5 and a globalbuffer 6.

The memory cell array 1 comprises a plurality of memory cells. Eachmemory cell is NAND type, for example, and has a storage capacity of 1byte. Logically speaking, those memory cells are arranged in the form ofa matrix having 16384 rows and 528 columns. Accordingly, the entirememory cell array 1 has a storage capacity of 8.65 megabytes.

The memory cell array 1 has eight data input-output terminals Tdata,16384 row control input terminals Trowcont each being connected incommon to the memory cells of the corresponding row, a read controlterminal Treadcont and a write control terminal Twritecont both beingcommon to all memory cells, and an erase control circuit 1 e for erasingdata.

When a control signal is supplied to a row control input terminalTrowcont while a control signal is being input to the read controlterminal Treadcont of the memory cell array 1, the first and subsequentmemory cells of the row supplied with the control signal output theirstorage contents 528 times in sequence by the amount (i.e., 1 byte)corresponding to one memory cell at a time to a data input-outputterminal Tdata.

On the other hand, while the control signal is being input to the writecontrol terminal Twritecont, the first and subsequent memory cellssequentially store, 528 times by 1 byte at a time, data which has beeninput from the data input-output terminal Tdata.

However, since each memory cell is NAND type, data recording can beperformed only in the direction of changing a stored value from “1” to“0”, and a memory cell whose stored value has been set at “0” oncemaintains the state of the stored value being “0” until the reset of thestorage contents.

As shown in FIG. 2, each row in the matrix of memory cells forms a pagehaving a storage capacity of 528 bytes. Serial page addresses 1 through16384 are assigned to pages, while serial addresses 1 through 528 areassigned to memory cells contained in each page.

As shown in FIGS. 2 and 3, each block comprises 16 pages. Each block hasa storage capacity of 8 kilobytes, and the entire storage area comprises1024 blocks.

Moreover, each page has a data area which occupies an area formed of thefirst to 512^(th) bytes and a redundant portion which occupies theremaining 16 bytes. The essential data is stored in the data area, whilean error check code, etc. are stored in the redundant portion.

And when a control signal as an instruction to erase data from aspecific block is input to the erase control circuit 1 e for data erase,the storage contents of all memory cells contained in the aforementionedblock are reset (i.e. the value stored in each memory cell becomes “1”).

The memory cell array 1 contains an empty block table and an addresstranslation table stored therein for accessing the memory cell array 1.

The top page of an arbitrary block of the memory cell array 1 stores theempty block table that stores information showing which blocks of thememory cell array 1 are empty blocks (i.e., blocks in a reset state andcontaining no memory cells in which data “0” has been stored).Information on the block having the empty block table stored therein isstored in the control circuit 5, as will be explained later.

An example of the structure of the empty block table when the memorycell array 1 has 1024 blocks in total is illustrated in FIG. 4. Thisempty block table is made up of memory cells of the first 128 bytes(i.e., the first to 1024^(th) bits) at the top of a specific block, andthe first to 1024^(th) bits which are in one-to-one correspondence withblocks 1 to 1024 store “1” when the corresponding blocks are emptyblocks, and store “0” when the corresponding blocks are not emptyblocks.

The address translation table, stored in the second and subsequent pagesof the block having the empty block table stored therein, storesinformation representing logical addresses assigned to the individualblocks of the memory cell array 1.

When the storage device is subjected to reading and writing by theoperations which will be explained later, a CPU (Central ProcessingUnit)12 included in an external computer 11, which will be explainedlater, and the controller 20, etc. recognize the logical addresses as aunit of data to be read or written.

The total capacity of areas to which the logical addresses have beenassigned corresponds to a predetermined value smaller than the storagecapacity of the memory cell array 1, the predetermined value being 16000pages, for example, while the storage area occupied by each logicaladdress corresponds to the storage area occupied by one page, forexample.

Specifically, in the case where a virtual storage area, having the size(e.g. 16000 pages) corresponding to a predetermined value smaller thanthe storage capacity of the memory cell array 1, is divided intosections each being 512 bytes and when serial numbers beginning with 0are assigned to the aforementioned sections, those serial numbers, i.e.,LBAs (Logic Block Addresses), serve as the logical addresses.

An example of the structure of the address translation table isillustrated in FIG. 5. The address translation table contains aplurality of records, a logical address is stored at the head of eachrecord, and the number (block address) assigned to a block in which thetop page of an area associated with the logical address is located andthe number assigned to the top page are stored following the logicaladdress.

As illustrated in FIG. 1, the I/O buffer 2 is connected to the globalbuffer 6, the data input-output terminals Tdata of the memory cell array1 and the control circuit 5.

In accordance with instructions from the control circuit 5, the I/Obuffer 2 performs the operation of outputting, by 1 byte at a time, datastored in the global buffer 6 to the data input-output terminals Tdataof the memory cell array 1, as well as the operation of outputting, by 1byte at a time, data which has been output from the data input-outputterminals Tdata, to the global buffer 6.

The X address buffer 3X, to which a row address signal representing arow address (i.e., a page address) of the memory cell array 1 has beeninput from the global buffer 6, outputs the row address to the X addressdecoder 4X.

The X address decoder 4X supplies a control signal having an activelevel to the row control input terminal Trowcont for the row specifiedby the row address signal or designated by the control circuit 5.

The block address buffer 3B, to which a block address signalrepresenting an address of each block of the memory cell array 1 hasbeen input from the global buffer 6, outputs the block address signal tothe block address decoder 4B.

The block address decoder 4B supplies, to the erase control circuit 1 e,a signal representing an instruction to erase data from the blockspecified by the block address signal or designated by the controlsignal 5.

The control circuit 5, to which a command is input from the globalbuffer 6, analyzes the command and controls the X address buffer 3X, theX address decoder 4X, the block address decoder 4B and the I/O buffer 2in accordance with the result of the analysis.

Furthermore, a write signal Swrite and a latch signal Slatch aresupplied to the control circuit 5 from the controller 20. And thecontrol circuit 5 controls the memory cell array 1 and the global buffer6 in accordance with those signals, as will be explained later.Moreover, the control circuit 5 supplies a busy signal Sbusy and a readysignal Sready to the controller 20 at the timing which will be explainedlater.

Further, when data stored in the global buffer 6 represents apredetermined command such as a setup command, an erasing command or thelike which will be explained later, the control circuit 5 executes theprocess designated by the command.

In addition, the busy signal Sbusy and the ready signal Sready may betransmitted through the same signal line. Then, for example, the controlcircuit 5 may supply the busy signal Sbusy in the case where the controlcircuit 5 applies a voltage representing a binary logic value “1” to apredetermined signal line, whereas in the case where the control circuit5 applies a voltage representing a binary logical value “0”, the controlcircuit 5 may supply the ready signal Sready.

The global buffer 6 is connected to the I/O buffer 2, the controlcircuit 5 and the controller 20. And the global buffer 6 stores, ofsignals on the bus line 13 and the storage contents of the I/O buffer 2,one which is being supplied to the global buffer 6 itself at the time ofthe supply of the control signal output from the control circuit 5, andoutputs the contents as stored to the X address buffer 3X or the controlcircuit 5, in accordance with the aforementioned control signal.

The controller 20 comprises a CPU, etc., and is connected to the controlcircuit 5 of the flash memory unit 10, and is connected also to theglobal buffer 6 of the flash memory unit 10 and the CPU 12 of thecomputer 11 via the bus line 13. However, the CPU which the controller20 comprises may be identical with the CPU 12 of the computer 11;

In accordance with a command supplied from the CPU 12 or the like whichthe external computer 11 comprises, the controller 20 supplies the writesignal Swrite and the latch signal Slatch to the control circuit 5 aswill be explained later, and supplies a physical address, to-be-writtendata, a command, etc. to the global buffer 6, in order to control theflash memory unit 10.

Furthermore, the controller 20 stores data representing the locations ofthe address translation table, the location of the empty block table andthe location of the block which has undergone writing most lately, andrefers to the data which the controller 20 has stored in itself, whenexecuting a process which will be explained later in accordance with acommand supplied from the CPU 12. Moreover, when the amount (i.e., thenumber of bytes) of to-be-written data, expressed in units of bytes, issupplied to the controller 20 from the CPU 12, the controller 20 storesand refers to the aforementioned amount during a process which will beexplained later.

(Operation of First Embodiment)

A process for writing data in this storage device will now be explainedwith reference to FIGS. 6 to 10.

FIG. 6 is a flowchart showing a data reading process;

FIG. 7 is a flowchart showing a physical address determining process;

FIG. 8 is a flowchart showing a writing process;

FIG. 9 is a flowchart showing an old data erasing process; and

FIG. 10 is a flowchart showing a process for updating the empty blocktable and the address translation table.

(Data-Reading)

In the case of reading data from this storage device, the CPU 12 withinthe computer 11 executes the data reading process shown in FIG. 6.

When the process is started, the CPU 12 outputs, onto the bus line 13, alogical address where to-be-read data has been stored, and supplies thecontroller 20 with a data read command and the number of pages of thestorage area in which the to-be-read data has been stored (FIG. 6, astep S101).

In response to the command from the CPU 12, the controller 20 acquiresthe logical address and the page number supplied through the bus line13, and stores both of them (a step S102).

Then, the controller 20 supplies the physical address of the top page ofthe address translation table to the global buffer 6, sends the latchsignal Slatch to the control circuit 5, and waits for the supply of theready signal Sready from the control circuit 5 (a step S103).

In response to the latch signal Slatch from the controller 20, thecontrol circuit 5 starts supplying the busy signal Sbusy to thecontroller 20 and sends, to the global buffer 6, an instruction to latchthe physical address which the controller 20 is supplying. In responseto this instruction, the global buffer 6 latches the physical addresswhich the controller 20 is supplying (a step S104). Of the physicaladdress latched by the global buffer 6, a portion corresponding to ablock address is supplied to the block address decoder 4B through theblock address buffer 3B, while a portion corresponding to a page addressis supplied to the X address decoder 4X through the X address buffer 3X.

In order to read the address translation table, the control circuit 5gives an instruction to select a page specified by the page address tothe X address decoder 4X to which the page address has been suppliedfrom the global buffer 6.

In response to the instruction from the control circuit 5, the X addressdecoder 4X outputs a control signal having an active level to a rowcontrol input terminal Trowcont destined for a page where the addresstranslation table has been stored. By so doing, that page of the addresstranslation table which has been designated by the controller 20 isselected.

Next, the control circuit 5 sends a data read instruction to the readcontrol terminal Treadcont of the memory cell array 1, stops the supplyof the busy signal Sbusy, and supplies the ready signal Sready to thecontroller 20. Meanwhile, the memory cell array 1 sequentially outputs,by 1 byte at a time, the storage contents of the aforementioned page ofthe address translation table to the controller 20 through the I/Obuffer 2 and the global buffer 6.

Meanwhile, the controller 20 reads each logical address stored in theaforementioned page and the physical address associated with eachlogical address by sequentially reading information supplied from theglobal buffer 6 (a step S105).

Then, the controller 20 determines whether the individual logicaladdresses read from the address conversion table include a logicaladdress which matches with the logical address acquired in the step S102from the CPU 12 (a step S106).

When the controller 20 determines the absence of a matching logicaladdress in the step S106, the controller 20 supplies the physicaladdress of the next page of the address translation table to the globalbuffer 6 and sends the latch signal Slatch to the control circuit 5 (astep S107), and this storage device returns the process to the stepS104.

On the other hand, when the controller 20 determines the presence of amatching address in the step S106, the storage device advances theprocess a step S108.

In the step S108, the controller 20 supplies, to the global buffer 6,the value of a physical address (i.e., the physical address of the topone of pages containing to-be-read data) shown by the logical addressdetermined as being a matching address in the step S106, and s end s thelatch signal Slatch to the control circuit 5.

Then, the flash memory unit 10 performs substantially the same procedureas that in the case of responding to the latch signal which thecontroller 20 has supplied in the step S103, and the flash memory unit10 sequentially supplies, by 1 byte at a time, the contents stored atthe physical address which the controller 20 has supplied to the globalbuffer 6 (i.e., the contents of the top page of an unread part of theto-be-read data) to the controller 20 via the global buffer 6 (a stepS109).

Meanwhile, the controller 20 reads the to-be-read data by sequentiallyreading information supplied sequentially from the global buffer 6 inthe step S109, and supplies the read data to the CPU 12 through the busline 13 (a step S110).

And the controller 20 determines whether the number of pages read afterthe start of the processing of the step S108 has reached the page numbersupplied from the CPU 12 and which the controller 20 has stored initself during the step S102 (a step S111).

And when the controller 20 determines that the number of pages has notyet reached the aforementioned page number, the controller 20 suppliesthe next physical address where the to-be-read data has been stored tothe global buffer 6, and sends the latch signal Slatch to the controlcircuit 5 (a step S112). Then, this storage device returns the processto the step S109.

On the other hand, when the controller 20 determines that the number ofpages has reached the aforementioned page number, the controller 20notifies the CPU 12 about the end of reading by way of sending an endcode to the CPU 12 through the bus line 13 or sending a non-illustratedcontrol signal to the CPU 12, for example (a step S113).

When the CPU 12 detects the end of reading (a step S114), it terminatesthe reading process.

By the procedure of the steps S101 to S114, the location of the physicaladdress corresponding to a logical address is found through the use ofthe address translation table which the memory cell array 1 has storedin itself, and data present in that location is read sequentially.

In the case where there are a plurality of logical read addresses, theprocedure of the steps S101 to S114 is repeated the number of timescorresponding to the number of logical read addresses.

(Data Write: Determination of New Physical Address)

In the case of writing data in the memory cell array 1, this storagedevice conducts a physical address determining process shown in FIG. 7,and executes a procedure for determining physical data write addresses.

First of all, from the size of to-be-written data, for example, the CPU12 calculates the number of pages required for writing, on theassumption that the storage capacity of one page is 512 bytes, and theCPU 12 determines the logical write addresses.

Then, the CPU 12 sends, onto the bus line 13, the logical address havingthe smallest number assigned thereto among the logical write addresses,and sends a data write command to the controller 20 (a step S201).

In response to the command sent from the CPU 12 in the step S201, thecontroller 20 performs substantially the same procedure as that of thesteps S103 to S107 included in the process shown in FIG. 6 (S202).

Specifically, the contents of the address translation table are read outfrom the flash memory unit 10, and a determination is sequentiallyperformed as to whether the read contents include an address whichmatches with the logical address acquired from the CPU 12 in the stepS201, thereby specifying the physical address associated with thelogical address acquired from the CPU 12.

When the physical address is specified in the step S202, the controller20 stores the specified physical address (a step S203). Then, in orderto read the empty block table, the controller 20 supplies the physicaladdress of the empty block table to the global buffer 6, and sends thelatch signal Slatch to the control circuit 5 (a step S204).

As in the case where the latch signal Slatch is supplied in the stepS103, the control circuit 5 causes the X address decoder 4X to select apage which contains the empty block table.

And when the page is selected, the control circuit 5 sends a data readinstruction to the read control terminal Treadcont of the memory cellarray 1. Upon reception of the instruction, the memory cell array 1sequentially outputs, by 1 byte at a time, the storage contents of theaforementioned page containing the empty block table to the controller20 through the I/O buffer 2 and the global buffer 6.

And the controller 20 sequentially reads information supplied from theglobal buffer 6, thereby acquiring the empty block table (a step S205).

Next, based on the contents of the acquired empty block table, thecontroller 20 specifies a physical address belonging to an arbitraryempty block (a step S206), and determines to hereafter handle thephysical address, specified in the step S206, as that shown by a logicalwrite address.

However, any physical address which has already been specified in thestep S206 after the start of the process of FIG. 7 is not specified inthe step S206 again.

Furthermore, in the step S206, the block to which belongs the physicaladdress that has been specified in the step S206 after the start of theprocess of FIG. 7, is handled as an empty block even after data has beenwritten at the above-mentioned physical address.

Moreover, a physical address to which no logical address has beenassigned may be selected as a physical write address.

(Data Write: Writing into Flash Memory)

Having finished the processing of the step S206, the controller 20executes a writing process shown in FIG. 8.

That is, when the controller 20 specifies a physical address by theprocedure of the step S206, it supplies the specified physical addressto the global buffer 6 and sends the latch signal Slatch to the controlcircuit 5 (a step S211).

In response to the latch signal Slatch, the control circuit 5 stops thesupply of the busy signal Sbusy, and starts the supply of the readysignal Sready to the controller 20. Then, the control circuit 5 causesthe X address decoder 4X to select the physical address specified in thestep S206.

Meanwhile, in response to the ready signal Sready, the controller 20requests the CPU 12 to supply to-be-written data (a step S212), inresponse to which request the CPU 12 supplies the first 1 byte of theto-be-written data to the controller 20 through the bus line 13.

And the controller 20 stores and supplies, to the global buffer 6, theto-be-written data supplied from the CPU 12 through the bus line 13, andsends the write signal Swrite to the control circuit 5 (a step S213).

In response to the write signal Swrite, the control circuit 5 instructsthe global buffer 6 to latch the to-be-written data supplied to theglobal buffer 6, stops the supply of the ready signal Sready, andrestarts the supply of the busy signal Sbusy to the controller 20. Theglobal buffer 6 latches the data on the bus line 13 and stores it in theI/O buffer 2.

Then, the control circuit 5 instructs the I/O buffer 2 to output thedata stored in the I/O buffer 2 to a data input-output terminal Tdata.In response to the instruction, the I/O buffer 2 outputs the data whichthe global buffer 6 has stored in the I/O buffer 2 itself to the datainput-output terminal Tdata.

Next, the control circuit 5 outputs a write control signal having theactive level to the write control terminal Twritecont, in order to causethe memory cell array 1 to store the data which is being currentlyoutput to the data input-output terminal Tdata. In response to the writecontrol signal, the memory cell array 1 stores the data, which is beinginput to the data input-output terminal Tdata, in the first memory cellof the currently selected page.

Having output the write control signal having the active level to thewrite control terminal Twritecont of the memory cell array 1, thecontrol circuit 5 stops the supply of the busy signal Sbusy and restartsthe supply of the ready signal Sready to the controller 20. Upondetecting the restart of the supply of the ready signal Sready, thecontroller 20 advances the process to a step S214.

In the step S214, the controller 20 sends a signal to request thesubsequent data, and thereafter determines whether 512-byte data hasbeen written in the currently selected page, with reference to the valueof a byte counter.

And when the controller 20 determines that 512-byte data has beenwritten, it requests the CPU 12 to send the next logical address (a stepS215).

Then, the CPU 12 sends the next logical address onto the bus line 13,and when the controller 20 acquires the logical address, the controller20 determines to handle the logical address as one acquired in the stepS201, and returns the process to the step S202 included in the processof FIG. 7.

On the other hand, when the controller 20 determines that 512-byte datahas not been written, the controller 20 sends a signal to request thesubsequent data to be written to the CPU 12 (a step S216).

In response to this signal, the CPU 12 determines whether there is anysubsequent data to be written, and when the CPU 12 determines that thereis no subsequent data, it supplies a control code representing the endof writing to the bus line 13. On the other hand, when the CPU 12determines that there is the subsequent data, it supplies the subsequent1-byte data to the bus line 13.

When the subsequent data or the control code representing the end ofwriting is supplied from the CPU 12 after the controller 20 has sent asignal to request the subsequent data in the step S206, the controller20 determines whether the supplied one is the control code representingthe end of writing (a step S217).

When the controller 20 determines that the supplied one is not thecontrol code, it returns the process to the step S213, whereas when thecontroller 20 determines that the supplied one is the control code, itgoes to an old data erasing process shown in FIG. 9.

In addition, a method by which the CPU 12 notifies the controller 20 ofthe absence of the to-be-written data is arbitrary and is not limited tothe supply of the control code through the bus ine 13; for example, acontrol signal representing the absence of the to-be-written data may besent to the controller through any other arbitrary control line.

(Data Write: Old Data Erase)

The controller 20, which has acquired the control code representing theend of writing, executes the old data erasing process shown in FIG. 9.

Upon start of the process shown in FIG. 9, the controller 20 firstlyspecifies a physical address belonging to the same block as that of thephysical address (i.e., the old physical address which had beenassociated with a logical write address until a new physical address wasbrought into association with the logical write address in the stepS206) that the control 20 has s to red in itself during the step S203,based on the contents of the address translation table which has beenread already (a step S221).

And this storage device uses each physical address specified in the stepS221 as one representing the top page of the to-be-written data, andperforms data reading in regard to each physical address by theprocedure of the steps S108 to S114 shown in FIG. 6 (a step S222).Furthermore, the controller 20 conducts substantially the same procedureas that of the steps S204 to S206, and specifies a physical addresswhere the data read by the step S222 is to be stored (a step 223).

In the step S223, however, the controller 20 does not specify a physicaladdress belonging to the same block as that in which the read data hasbeen stored.

Next, this storage device writes the data read by the step S222 at thephysical address specified by the step S223, in accordance with theprocess shown in FIG. 8 (a step S224).

Following the above, the controller 20 supplies, to the global buffer 6,a predetermined setup command for specifying a block from which thestorage contents are to be erased, and sends the latch signal Slatch tothe control circuit 5 (a step S225).

The control circuit 5, when the latch signal Slatch is supplied theretoby the step S225, detects that the data supplied to the global buffer 6is the setup command, and determines to handle data, which will besupplied to the global buffer 6 next, as the block address of the blockfrom which the storage contents are to be erased.

Then, the controller 20 supplies, to the global buffer 6, the blockaddress of the block (i.e., the block to which belongs the physicaladdress that the controller 20 has stored in itself during the stepS203) from which the storage contents are to be erased, and sends thelatch signal Slatch to the control circuit 5 (a step S226).

In response to the latch signal Slatch supplied in the step S226, thecontrol circuit 5 sends an instruction to the global buffer 6 so as tocause the global buffer 6 to latch the block address which thecontroller 20 is supplying. The block address latched by the globalbuffer 6 is supplied to the block address decoder 4B through the blockaddress buffer 3B, whereby the block from which the storage contents areto be erased is selected.

Next, the controller 20 supplies a predetermined erase command forerasing the storage contents to the global buffer 6, and sends the latchsignal Slatch to the control circuit 5 (a step S227).

The control circuit 5, when the latch signal Slatch is supplied theretoin the step S227, detects that the data supplied to the global buffer 6is the erasing command, and instructs the block address decoder 4B toerase the storage contents of the selected block.

The block address decoder 4B which has received the instruction sends,to the erase control circuit 1 e, a signal representing an instructionto erase data from the block selected as an erasing target. As a result,the storage contents of the aforementioned block are erased.

By the procedure of the steps S221 to S227, data recorded in the memorycell array 1 is erased, and data stored in the same block as that of theerased data is saved to other pages.

In addition, the old data erasing process is not necessarily performedafter the writing process. For example, therefore, after a physical datawrite address is determined, the storage contents of a block with an oldphysical address, which had been associated with a logical address untilthe logical address was newly brought into association with the physicaldata write address, may be deleted first, and then new data may bewritten at the physical data write address.

Moreover, the scene wherein data erase is effected is not limited tothat wherein data erase is performed as a part of the data writingprocess as in the case of the above-described steps S221 to S227.

Therefore, data erase can be performed without the writing of new databeing involved.

To be specific, the CPU 12, for example, firstly sends a data erasecommand to the controller 20, and supplies a logical erase address tothe controller 20 through the bus line 13.

In response to the command, the controller 20 conducts the sameprocedure as that of the steps S201 to S203 included in the process ofFIG. 7, and specifies a physical address (i.e., a physical eraseaddress) designated by the logical erase address.

And the controller 20 handles the specified physical erase address asthat specified by the step S203, and conducts the procedure of theaforementioned steps S221 to S227. By so doing, the storage contents ofthe block to which the physical erase address belongs are erased.

In addition, in the case of designating new physical write addresses inthe above-described data writing process, the controller 20 maydesignate the new physical write addresses so that data can besequentially written in the blocks following the empty block in whichdata has been written last time and so that when those blocks include noempty block, data may be sequentially written in any empty blocksfollowing the top block.

Due to this, since empty blocks undergo writing cyclically, a specificblock does not frequently undergo data update, avoiding the situation inwhich the performance of the specific block only is deteriorated.

(Update of Empty Block Table and Address Translation Table)

When data erase and data write are completed by the above-describedprocedures, the controller 20 initiates the process shown in FIG. 10 inorder to update the empty block table and the address translation table.

In the process of FIG. 10, in order to acquire the empty block tablefrom the flash memory unit 10, the controller 20 firstly conducts thesubstantially the same procedure as that of the steps S201 to S205 shownin FIG. 7, and stores the empty block table temporarily (a step S301).

Then, based on the contents of the temporarily stored empty block table,the controller 20 specifies one empty block in order to newly write theempty block table and the address translation table, and stores the toppage of that block (a step S302).

Then, of the temporarily stored empty block table, the controller 20translates, from “1” to “0”, bits representing the empty block in whichdata has been written and the empty block specified by the step S302, aswell as bits representing the blocks to which the physical addressesspecified by the steps S206 and S223 belong. Furthermore, the controller20 translates, from “0” to “1”, a bit representing the block in whichthe empty block table and the address translation table are presentcurrently and a bit representing the block whose storage contents havebeen erased by the step S227 (a step S303).

Next, the controller 20 supplies the physical address of the top page ofthe block specified by the step S302 to the global buffer 6, and sendsthe latch signal Slatch to the control circuit 5 (a step S304).

In response to the latch signal Slatch, the control circuit 5 stops thesupply of the busy signal Sbusy, and starts the supply of the readysignal Sready to the controller 20. And the control circuit 5 causes theX address decoder 4X to select the physical address supplied from thecontroller 20 to the global buffer 6.

Meanwhile, in response to the ready signal Sready, the controller 20supplies the first 1 byte of the empty block table translated by thestep S303 to the global buffer 6 (a step S305), and sends the writesignal Swrite to the control circuit 5 (a step S306).

In response to the write signal Swrite, the control circuit 5 causes theglobal buffer 6 to latch the data supplied from the controller 20 to theglobal buffer 6, stops the supply of the ready signal Sready, andrestarts the supply of the busy signal Sbusy to the controller 20. Theglobal buffer 6 latches the data on the bus line 13, and stores it inthe I/O buffer 2.

Next, the control circuit 5 causes the I/O buffer 2 to supply the datawhich the I/O buffer 2 has stored to a data input-output terminal Tdata,supplies the write control signal having the active level to the writecontrol terminal Twritecont, and records the data which is beingsupplied to the data input-output terminal Tdata in the first memorycell of the currently selected page.

And the control circuit 5 stops the supply of the busy signal Sbusy, andrestarts the supply of the ready signal Sready to the controller 20.

When the controller 20 detects the restart of the ready signal Sready,it determines whether any part of the empty block table, which thecontroller 20 has stored in itself, remains unsupplied to the flashmemory unit 10 (a step S307).

And when the controller 20 determines that any part of the empty blocktable remains unsupplied, the controller 20 supplies the subsequent 1byte of the empty block table, which the controller 20 has temporarilystored in itself, to the global buffer 6 (a step S308) and returns theprocess to the step S306.

On the other hand, when the controller 20 determines that no part of theempty block table remains unsupplied, the controller 20 supplies thephysical address of the top page of the address translation table to theglobal buffer 6 in order to update the address translation table,supplies the latch signal Slatch to the control circuit 5, and waits forthe supply of the ready signal Sready from the control circuit 5 (a stepS309).

Then, the flash memory unit 10 stops the supply of the busy signalSbusy, supplies the ready signal Sready to the controller 20, andprovides the controller 20 with the storage contents of that page of theaddress translation table which has been designated by the controller20, as in the case where of the supply of the latch signal in the stepS103.

Meanwhile, similarly in the step S105, the controller 20 reads, from theflash memory unit 10, each logical address stored in the pagecorresponding to the physical address which the controller 20 itself hassupplied and the physical address associated with each logical address,and the controller 20 temporarily stores the read addresses (a stepS310).

Then, the controller 20 determines whether the temporarily storedlogical addresses include an address which matches with the logicaladdress which the controller 20 has stored in itself as a target whosephysical address allocation needs to be changed (a step S311).

When the controller 20 determines that they include no matching address,the controller 20 advances the process to a step S313. When thecontroller 20 determines that they include a matching address, thecontroller 20 translates, among the physical addresses which thecontroller 20 has temporarily stored in itself, the physical addressassociated with the logical address determined as being the matchingaddress into one which is to be newly associated with the logicaladdress (a step S312), and advances the process to the step S313.

In the step S311, the logical address that the CPU 12 has supplied tothe controller 20 as a data write address, for example, is determined asan address matching with the logical address which the controller 20 hasstored as the target whose physical address allocation needs to bechanged. Then, in the step S312, the physical address designated by theaforementioned logical address is translated from the old physicaladdress specified by the step S202 into the new physical addressspecified by the step S206.

Then, this storage device performs substantially the same procedure asthat of the steps S301 to S308, whereby that 1-page portion of theaddress translation table which the storage device has stored in itselfis written in the page following that page of the memory cell array 1which has undergone writing most lately after the start of the processshown in FIG. 10 (a step S313).

Upon completion of writing, the controller 20 determines whether thenumber of pages as written in the step S313 is equal to the total numberof pages of the address translation table, thereby determining whetherthe writing of the address translation table has been completed or not(a step S314).

When it is determined that the writing of the address translation tablehas been completed, the process is advanced to a step S316. When it isdetermined that the writing of the address translation table has not yetbeen completed, the physical address of the next page of the addresstranslation table is supplied to the global buffer 6, the latch signalSlatch is sent to the control circuit 5 (a step S315), and the processis returned to the step S310.

In the step S316, the controller 20 stores the locations of the emptyblock table and address translation table after updated.

And this storage device erases the storage contents from the logicaladdresses where the empty block table and the address translation tablebefore updated are present (a step S317).

Incidentally, according to this storage device, the correspondencebetween the logical and physical addresses of data is written in theaddress translation table in the data writing order. At the time ofreading the data, the correspondence between the logical and physicaladdresses is read while sequentially searching the address translationtable. However, the following speedy method can also be employed to readthe correspondence between the logical and physical addresses.

For example, using a predetermined hash function, the controller 20 mayderive the location at which the correspondence between the logical andphysical addresses is to be stored in the address translation table froma logical address which is sent from the CPU 12 at the data writingtime, and the controller 20 may control the flash memory unit 10 so asto store the correspondence between the logical and physical addressesat the derived location. And using the aforementioned hash function alsoat the data- reading time, the controller 20 may derive the storagelocation of the correspondence between the logical and physicaladdresses from the logical address sent from the CPU 12, and may readthe physical address from the location in the flash memory unit 10 whichlocation has been derived by the controller 20 itself.

In this case, collision can occur at the storage location derived fromthe logical address sent from the CPU 12; in that case, however, thecorrespondence between the logical and physical addresses may be storedin the storage location next to the derived storage location, or anyspecial area may be provided for storage in the case of collision.

As explained above, according to this storage device, the addresstranslation table and the empty block table are stored in the memorycell array 1, and data can be read and written using those tables.

In addition, the size of each block is not limited to that describedpreviously. For example, each block is not necessarily constituted by 16pages, and the size of each block needs only be equal to an integermultiple of the size of each page, for example.

Furthermore, in the case where this storage device is a flash memorycomprising a JEIDA/PCMCIA interface, for example, the size of each pageis, in general, determined by the OS (Operating System) which isexecuted on the computer 11, but the size of each page may notnecessarily be determined by the OS.

Moreover, in general, the size of each block is a value peculiar to thisstorage device, but the size of each block in this storage device can bedesignated by an external control.

(Second Embodiment)

In the storage device of the first embodiment, information representingthe locations of empty blocks is stored concentrically in a specificarea. However, the information representing the locations of the emptyblocks is not necessarily stored concentrically in a specific area, andeach empty block may sequentially store the information representing thelocation of another empty block so that the management of the emptyblocks can be performed in the manner of chaining the empty blocks.

The storage device of the second embodiment, comprising the empty blocksthus chained, and a process for managing the empty blocks, will now bedescribed with reference to FIGS. 11 to 13.

The basic structure of the storage device according to this embodimentis substantially the same as that of the storage device according to thefirst embodiment. In this embodiment, however, the address translationtable is stored in the top area of an arbitrary blocks.

Moreover, in a predetermined location within a redundant portion of eachempty block, empty block information representing the number thatspecifies the nearest one of the empty blocks which are, logicallyspeaking, located after t he aforementioned empty block, is stored asshown in FIG. 11.

A chain of empty blocks, which chain is defined by the empty blockinformation, differs in order from a physical arrangement of emptyblocks. Further, the control circuit 5 stores the empty block numberspecifying the first one of the empty blocks forming the chain. In thestorage device of this embodiment, a data area and a redundant portionare arranged in each page so as not to overlap with each other asexplained previously.

Due to this, even if the process of writing data in an empty block inwhich the empty block information has already been written is executedby simply overwriting the data, the empty block information written inthe redundant portion of the aforementioned empty block is notdestroyed.

(Operation of Second Embodiment)

The procedures for writing data in this storage device are the same asthose of the first embodiment, except the data writing process and theprocess for updating the empty block information and the addresstranslation table. Therefore, the operation of this storage deviceduring mainly the data writing process and the process for updating theempty block information and the address translation table, will now beexplained with reference to FIGS. 12 to 13.

(Data Write)

The process for writing data in this storage device starts from a step501 shown in FIG. 12.

In the step S501, the CPU 12 specifies logical write addresses, afterwhich the CPU 12 supplies, onto the bus line 13, the value of thelogical address whose number is smallest among the specified logicalwrite addresses, and provides a data write command with the controller20.

In response to the command supplied in the step S501, the controller 20stores, as a logical write address, the logical address supplied fromthe CPU 12 through the bus line 13 (a step S502).

Subsequently, the controller 20 performs substantially the sameprocedure as that of the step S202 mentioned previously, therebyspecifying the physical address associated with the logical writeaddress which the controller 20 has stored in itself (a step S503).

Then, the controller 20 specifies the top page of the top empty blockwith reference to data which the controller 20 has stored in itself (astep S504). And the controller 20 determines to hereafter handle thephysical address specified by the step S503 and a physical addressbelonging to the page specified by the step S504, with both physicaladdresses being replaced with each other (a step S505). As a result, thephysical address specified by the step S504 and belonging to an emptyblock located at the top of the chain becomes to serve a physical writeaddress.

Next, the controller 20 supplies the physical address determined asbeing the write address in the step S505 to the global buffer 6, andinstructs the control circuit 5 to read the 513^(th) and subsequentbytes of the page designated by the aforementioned physical address (astep S506).

The control circuit 5 instructs the X address decoder 4X to select thepage specified by the step S504, and thereafter sends a data readinstruction to the read control terminal Treadcont of the memory cellarray 1. The memory cell array 1 sequentially supplies, by 1 byte at atime, the empty block information stored in the redundant portion of theaforementioned page to the controller 20 through the I/O buffer 2 andthe global buffer 6.

When the controller 20 has read the empty block information suppliedfrom the flash memory unit 10, the controller 20 stores the empty blockinformation as information on the location of the top empty block (astep S507). The empty block information stored in the step S507represents the empty block which newly comes out at the top of the chainas a result of the process shown in FIG. 12.

Subsequently, this storage device performs substantially the sameprocedure as that of the above-described steps S211 to S217 in order towrite data, while handling the physical address belonging to the pageand specified as being the write address in the step S505, as thephysical address specified by the step S206 of the first embodiment (astep S508).

And the controller 20 terminates the data writing process when thecontroller 20 determines, in the procedure which corresponds to the stepS217 among the procedures carried out in the step S508, that the controlcode representing the end of writing has been supplied from the CPU 12.

Furthermore, when the controller 20 determines in the procedurecorresponding to the step S214 that 512-byte data has been written atthe currently selected page, the controller 20 sends a signal requestingthe supply of the next logical address to the CPU 12, in response towhich signal the CPU 12 sends the next logical address onto the bus line13. And when the controller 20 acquires the next logical address fromthe CPU 12 through the bus line 13, the controller 20 stores the logicaladdress as the logical write address, overwriting the logical address onthe previously stored logical address, and returns the process to thestep S503.

By the procedure of the steps S501 to S508 described above, the physicaladdress designated by the logical write address is specifiedsequentially from the top of the chain of empty blocks, and data iswritten in the empty blocks as specified.

(Updating of Empty Block Information and Address Translation Table)

When updating the empty block information and the address translationtable, the controller 20 initiates the process of FIG. 13 from a stepS601.

In the process shown in FIG. 13, the controller 20 firstly specifies thetop page of the top empty block, with reference to data which thecontroller 20 has stored in itself (a step S601).

Next, the controller 20 supplies the physical address of the pagespecified by the step S601 to the global buffer 6, and sends the latchsignal Slatch to the control circuit 5 (a step S602).

In response to the latch signal Slatch, the control circuit 5 instructsthe X address decoder 4X to select the page designated by the physicaladdress supplied to the global buffer 6, and sends the data readinstruction to the read control terminal Treadcont of the memory cellarray 1 when the page is selected. The memory cell array 1 sequentiallyoutputs, by 1 byte at a time, the storage contents of the aforementionedpage to the controller 20 through the I/O buffer 2 and the global buffer6.

And the controller 20 sequentially reads the 513^(th) and subsequentbytes of the storage contents supplied from the global buffer 6, therebyacquiring the empty block information stored in the redundant portion ofthe read page (a step S603).

Having read the empty block information, the controller 20 overwritesthe empty block information on information concerning the top page ofthe top empty block specified by the step S601. In other words, thecontroller 20 updates or replaces information concerning the location ofthe top empty block with information concerning the location of the nextempty block (a step S604).

Next, the controller 20 updates the address translation table byexecuting the procedure of the above-described steps S309 to S315 (astep S605), and stores the location of the updated address translationtable (a step S606).

However, the address translation table after updated is written in thelogical address corresponding to the currently selected page specifiedby the step S601. Further, the information to be updated includes notonly information concerning a physical block to which a new logicaladdress has been assigned, but also information concerning the result ofthe physical address replacement performed in the step S505.

Next, in order to add the empty block information, the controller 20refers to the data stored in itself and specifies the top page of thetop empty block (a step S607).

Following the above, the controller 20 sends the physical address of thepage which the controller 20 itself is specifying currently to theglobal buffer 6, and sends the latch signal Slatch to the controlcircuit 5 (a step S608).

In response to the latch signal Slatch, the control circuit 5 causes theX address decoder 4X to select the page designated by the physicaladdress supplied to the global buffer 6, and sends the data readinstruction to the read control terminal Treadcont of the memory cellarray 1 so as to cause the memory cell array 1 to send the storagecontents of the aforementioned page to the controller 20 through the I/Obuffer 2 and the global buffer 6.

Then, the controller 20 sequentially reads the 513^(th) and subsequentbytes of information supplied from the global buffer 6, therebyacquiring information stored in the redundant portion of theaforementioned page (a step S609).

Next, the controller 20 determines whether the empty block informationis contained in the information read by the step S609 (a step S610).

When the empty block information is contained therein, the controller 20specifies the top page of the next empty block designated by the emptyblock information (a step S611), and returns the process to the stepS608.

When no block information is contained therein, the currently specifiedpage is the top page of the last empty block.

At that time, the controller 20 conducts substantially the sameprocedure as that of the above-described steps S301 to S308, andcontrols the flash memory unit 10 so that data including information onthe block whose first to 512^(th) bytes are empty and whose 513^(th) andsubsequent bytes currently store, as the empty block information, theold address translation table before updated, is written in thecurrently selected page (a step S612).

By so doing, the block in which the old address translation block isstored currently is incorporated into the end of the chain of emptyblocks.

Subsequently, this storage device erases the storage contents of theblock which contains the address translation table before updated, inaccordance with the same procedure as that of the above-described stepsS221 to S227 (a step S613). As a result, the block in which the oldaddress translation block has been stored becomes an empty block.

By the procedure of the steps S601 to S613 described above, the emptyblock information and the address translation table are updated.

In addition, when initializing the memory cell array 1, the controller20 erases the contents of all blocks of the memory cell array 1 once,and thereafter controls the flash memory unit 10 so as to write emptyblock chain information in the redundant portion of each block.

In this case, the controller 20 writes the chain information so that theempty blocks are chained randomly as shown in FIG. 11. If data writinglocations are distributed by thus designing the chain information, thesituation in which data is repeatedly written in a specific area onlycan be prevented.

In addition, this invention is not limited to the above-describedembodiments, and various modifications and applications are possible.

For example, according to the above embodiments, in order to facilitateunderstanding, data is transferred in units of 1 byte between the CPU 12and the storage device. However, data can be transferred in arbitraryunits such as 2 bytes, 4 bytes, etc. Similarly, the capacity of thememory cells is not limited to 1 byte and may be 2 bytes or else.

Furthermore, the memory cell array 1 used in the storage devices of theabove-described embodiments is one chip only. However, this inventioncan be applied also to a storage device comprising plural-chip flashmemories. In this case, the address translation table (and the emptyblock table) may be stored in any one block of one of the plural-chipflash memories; furthermore, the controller 20 may store informationconcerning the chip having the address translation table (and the emptyblock table) stored therein. Moreover, in the case where the empty blockinformation is structured as the chain information as in the case of thesecond embodiment, the chain information which indicates the chip havingthe next empty block and the block number may be written in a redundantarea.

Further, according to the above embodiments, the memory cell array 1 isNAND type. However, it may be NOR type.

Moreover, according to the above embodiments, the control circuit 5 isarranged within the storage device. However, access to the memory cellarray 1 can be controlled without the use of the control circuit 5 bycausing the controller 20 and/or the CPU 12 to perform the operationswhich the control circuit 5 executes. Access to the memory cell array 1can also be controlled without the use of the controller 20 by causingthe CPU 12 to perform the operations which the controller 20 executes.

In the case where the CPU 12 executes the operations of the controlcircuit 5 and controller 20, a program for executing the above-describedcontrol operations is installed into the computer 11 from a medium (afloppy disk, a CD-ROM or the like) containing the program storedtherein, and the program is run on an OS (Operating System) to executethe above-described processes.

According to this invention, as explained above, informationrepresenting the locations of the empty blocks and information showingthe correspondence between the logical and physical addresses, etc. arestored in a block erase type storage medium. This eliminates the need toprovide any other storage medium for storing the informationrepresenting the locations of the empty blocks and the informationshowing the correspondence between the logical and physical addresses.

What is claimed is:
 1. A storage device comprising: a non-volatilesemiconductor memory including a plurality of memory blocks to whichphysical addresses have been assigned; an erasure for batch erasing ofstored data from said memory in units of memory blocks; and a writer, towhich data and logical addresses are input, which determines locationswhere said data is to be stored in said memory and which writes saiddata in said locations; wherein said memory stores an addresstranslation table which stores information showing a correspondencebetween said logical addresses and physical addresses of said memory,wherein said writer adds, to said address translation table, informationshowing a correspondence between physical addresses of the locationswhere said data has been written and the input logical addresses, orupdates said address translation table, and wherein the data and theaddress translation table are both stored in said memory, said storagedevice further comprising a reader that performs the following steps:storing a physical address of a block in which said address translationtable has been written; accessing the block which contains said addresstranslation table stored therein and reading physical addressescorresponding to logical addresses of to-be-read data; and reading andoutputting data stored at the physical addresses read by said reader,wherein said memory stores an empty block table which stores informationspecifying empty blocks containing no data stored therein; said writercomprises empty block selector which accesses a block which containssaid empty block table stored therein and selects a writing target blockfrom the empty blocks registered in said empty block table, and emptyblock writer which writes to-be-written data in the empty block selectedby said empty block selector, said storage device further comprising: aneliminator which eliminates said empty block table which storesinformation specifying said empty block that existed until said emptyblock writer has written said data in said empty block; and an emptyblock updater which causes said memory to store said empty block tablewhich stores information specifying empty blocks that remain after saidempty block writer has written said data in said empty block.
 2. Thestorage device according to claim 1, wherein said memory stores saidaddress translation table and said empty block table in one block.
 3. Astorage device comprising: a non-volatile semiconductor memory includinga plurality of memory blocks to which physical addresses have beenassigned; an erasure for batch erasing of stored data from said memoryin units of memory blocks; and a writer, to which data and logicaladdresses are input, which determines locations where said data is to bestored in said memory and which writes said data in said locations;wherein said memory stores an address translation table which storesinformation showing a correspondence between said logical addresses andphysical addresses of said memory, wherein said writer adds, to saidaddress translation table, information showing a correspondence betweenphysical addresses of the locations where said data has been written andthe input logical addresses, or updates said address translation table,and wherein the data and the address translation table are both storedin said memory, wherein said memory stores an empty block table whichstores information specifying empty blocks containing no data storedtherein; and said writer comprises empty block selector which accesses ablock which contains said empty block table stored therein and whichselects a writing target block from the empty blocks registered in saidempty block table, and empty block writer which writes to-be-writtendata in the empty block selected by said empty block selector, saidstorage device further comprising: an eliminator which eliminates saidempty block table which stores information specifying said empty blockthat existed until said empty block writer has written said data in saidempty block; and an empty block updator which causes said memory tostore said empty block table which stores information specifying emptyblocks that remain after said empty block writer has written said datain said empty block.
 4. The storage device according to claim 3, whereinsaid memory stores said address translation table and said empty blocktable in one block.
 5. A storage device comprising: a non-volatilesemiconductor memory, including a plurality of memory blocks to whichphysical addresses have been assigned; an erasure which erases storeddata from said memory in units of memory blocks; and a writer, to whichto-be-written data and logical addresses are input, which determineslocations where said data is to be stored in said memory and writes saiddata in said locations; wherein said memory stores empty blockinformation specifying empty blocks in which said data is not stored,and wherein said writer writes said data in an empty block specified bysaid empty block information, wherein said writer further comprises anupdater which causes the empty block information stored in said storagemeans to the empty block information which specifies information onempty blocks that remain after said writer has written said data in saidempty block, wherein: said empty block information is stored in aportion of each empty block, and includes chain information registeredto specify another empty block in a chain manner; and said writerdetects an empty block in accordance with said chain information andwrites said data in said empty block.
 6. The storage device according toclaim 5, wherein said memory has data areas and redundant areas, andsaid chain information is stored in said redundant areas.
 7. A storagedevice comprising: a non-volatile semiconductor memory, including aplurality of memory blocks to which physical addresses have beenassigned; an erasure which erases stored data from said memory in unitsof memory blocks; and a writer, to which to-be-written data and logicaladdresses are input, which determines locations where said data is to bestored in said memory and writes said data in said locations; whereinsaid memory stores empty block information specifying empty blocks inwhich said data is not stored, and wherein said writer writes said datain an empty block specified by said empty block information, whereinsaid writer further comprises an updater which causes the empty blockinformation stored in said storage means to the empty block informationwhich specifies information on empty blocks that remain after saidwriter has written said data in said empty block, wherein: said emptyblock information is stored in a portion of each empty block, andincludes chain information registered to specify another empty block ina chain manner; and said writer comprises top empty block storage whichstores a physical address of a first empty block in a chain defined bysaid chain information, and a second writer writes said data in theempty block having said physical address assigned thereto and causessaid top empty block storage to store the chain information registeredin said block.
 8. The storage device according to claim 7, wherein saidmemory has data areas and redundant areas, and said chain information isstored in said redundant areas.
 9. A storage device comprising: anon-volatile semiconductor memory, including a plurality of memoryblocks to which physical addresses have been assigned; an erasure whicherases stored data from said memory in units of memory blocks; and awriter, to which to-be-written data and logical addresses are input,which determines locations where said data is to be stored in saidmemory and writes said data in said locations; wherein said memorystores empty block information specifying empty blocks in which saiddata is not stored, and wherein said writer writes said data in an emptyblock specified by said empty block information, wherein: said emptyblock information is stored in a portion of each empty block, andincludes chain information registered to specify another empty block ina chain manner; and said writer detects an empty block in accordancewith said chain information and writes said data in said empty block.10. The storage device according to claim 9, wherein said memory hasdata areas and redundant areas, and said chain information is stored insaid redundant areas.
 11. A storage device comprising: a non-volatilesemiconductor memory, including a plurality of memory blocks to whichphysical addresses have been assigned; an erasure which erases storeddata from said memory in units of memory blocks; and a writer, to whichto-be-written data and logical addresses are input, which determineslocations where said data is to be stored in said memory and writes saiddata in said locations; wherein said memory stores empty blockinformation specifying empty blocks in which said data is not stored,and wherein said writer writes said data in an empty block specified bysaid empty block information, wherein: said empty block information isstored in a portion of each empty block, and includes chain informationregistered to specify another empty block in a chain manner; and saidwriter comprises top empty block storage which stores a physical addressof a first empty block in a chain defined by said chain information, anda second writer which writes said data in the empty block having saidphysical address assigned thereto and causes said top empty blockstorage to store the chain information registered in said block.
 12. Thestorage device according to claim 11, wherein said memory has data areasand redundant areas, and said chain information is stored in saidredundant areas.
 13. A storage device comprising: storage means,including a plurality of memory blocks to which physical addresses havebeen assigned; erasure means for batch erasing of stored data from saidstorage means in units of memory blocks; and writing means, to whichdata and logical addresses are input, for determining locations wheresaid data is to be stored in said storage means and for writing saiddata in said locations; wherein said storage means stores an addresstranslation table which stores information showing a correspondencebetween said logical addresses and physical addresses of said storagemeans, said writing means comprises means for adding, to said addresstranslation table, information showing a correspondence between physicaladdresses of the locations where said data has been written and theinput logical addresses, or for updating said address translation table,and reading means including: means for storing a physical address of ablock in which said address translation table has been written; physicaladdress reading means for accessing the block which contains saidaddress translation table stored therein and for reading physicaladdresses corresponding to logical addresses of to-be-read data; andmeans for reading and outputting data stored at the physical addressesread by said physical address reading means; said storage means storingan empty block table which stores information specifying empty blockscontaining no data stored therein; said writing means comprising emptyblock selecting means for accessing a block which contains said emptyblock table stored therein and for selecting a writing target block fromthe empty blocks registered in said empty block table, and empty blockwriting means for writing to-be-written data in the empty block selectedby said empty block selecting means; and the storage device furthercomprising: means for eliminating said empty block table which storesinformation specifying said empty block that existed until said emptyblock writing means has written said data in said empty block; and emptyblock updating means, comprising means for causing said storage means tostore said empty block table which stores information specifying emptyblocks that remain after said empty block writing means has written saiddata in said empty block.
 14. The storage device according to claim 13,wherein said storage means stores said address translation table andsaid empty block table in one block.
 15. A storage device comprising:storage means, including a plurality of memory blocks to which physicaladdresses have been assigned; erasure means for batch erasing of storeddata from said storage means in units of memory blocks; and writingmeans, to which data and logical addresses are input, for determininglocations where said data is to be stored in said storage means and forwriting said data in said locations; wherein said storage means storesan address translation table which stores information showing acorrespondence between said logical addresses and physical addresses ofsaid storage means, and said writing means comprises means for adding,to said address translation table, information showing a correspondencebetween physical addresses of the locations where said data has beenwritten and the input logical addresses, or for updating said addresstranslation table; wherein: said storage means stores an empty blocktable which stores information specifying empty blocks containing nodata stored therein; and said writing means comprises empty blockselecting means for accessing a block which contains said empty blocktable stored therein and for selecting a writing target block from theempty blocks registered in said empty block table, and empty blockwriting means for writing to-be-written data in the empty block selectedby said empty block selecting means; and the storage device furthercomprising: means for eliminating said empty block table which storesinformation specifying said empty block that existed until said emptyblock writing means has written said data in said empty block; and emptyblock updating means, comprising means for causing said storage means tostore said empty block table which stores information specifying emptyblocks that remain after said empty block writing means has written saiddata in said empty block.
 16. The storage device according to claim 15,wherein said storage means stores said address translation table andsaid empty block table in one block.
 17. A storage device comprising:storage means, including a plurality of memory blocks to which physicaladdresses have been assigned; erasure means for batch erasing of storeddata from said storage means in units of memory blocks; and writingmeans, to which to-be-written data and logical addresses are input, fordetermining locations where said data is to be stored in said storagemeans and for writing said data in said locations; wherein said storagemeans stores empty block information specifying empty blocks in whichsaid data is not stored, and said writing means writes said data in anempty block specified by said empty block information; wherein: saidwriting means further comprises updating means for changing the emptyblock information stored in said storage means to the empty blockinformation which specifies information on empty blocks that remainafter said writing means has written said data in said empty block; saidempty block information is stored in a portion of each empty block, andincludes chain information registered to specify another empty block ina chain manner; and said writing means comprises means for detecting anempty block in accordance with said chain information and for writingsaid data in said empty block.
 18. The storage device according to claim17, wherein said storage means has data areas and redundant areas, andsaid chain information is stored in said redundant areas.
 19. Thestorage device according to claim 17, wherein: said empty blockinformation is stored in a portion of each empty block, and includeschain information registered to specify another empty block in a chainmanner; and said writing means comprises top empty block storing meansfor storing a physical address of a first empty block in a chain definedby said chain information, and means for writing said data in the emptyblock having said physical address assigned thereto and for causing saidtop empty block storing means to store the chain information registeredin said block.
 20. The storage device according to claim 19, whereinsaid storage means has data areas and redundant areas, and said chaininformation is stored in said redundant areas.
 21. The storage deviceaccording to claim 17, wherein: said empty block information is storedin a portion of each empty block, and includes chain informationregistered to specify another empty block in a chain manner; and saidwriting means comprises means for detecting an empty block in accordancewith said chain information and for writing said data in said emptyblock.
 22. The storage device according to claim 21, wherein saidstorage means has data areas and redundant areas, and said chaininformation is stored in said redundant areas.
 23. The storage deviceaccording to claim 17, wherein: said empty block information is storedin a portion of each empty block, and includes chain informationregistered to specify another empty block in a chain manner; and saidwriting means comprises top empty block storing means for storing aphysical address of a first empty block in a chain defined by said chaininformation, and means for writing said data in the empty block havingsaid physical address assigned thereto and for causing said top emptyblock storing means to store the chain information registered in saidblock.
 24. The storage device according to claim 23, wherein saidstorage means has data areas and redundant areas, and said chaininformation is stored in said redundant areas.
 25. The storage deviceaccording to claim 13, wherein each of said blocks includes a pluralityof memory pages, each of memory pages includes memory cells, and datacan be read from and written into the memory cells of each of the pagesin sequence.
 26. The storage device according to claim 15, wherein eachof said blocks includes a plurality of memory pages, each of memorypages includes memory cells, and data can be read from and written intothe memory cells of each of the pages in sequence.
 27. The storagedevice according to claim 17, wherein each of said blocks includes aplurality of memory pages, each of memory pages includes memory cells,and data can be read from and written into the memory cells of each ofthe pages in sequence.